5G infrastructure and the need for end-to-end programmability

“We are currently in a transition period for cellular connectivity, and the future of ubiquitous wireless connectivity is on the rise. Globally, the success of 2G, 3G and 4G has propelled mobile phone usage to an incredible 7.5 billion units. Shockingly, this puts more mobile devices than the world’s population. Perhaps even more impactful is the impact cellular connectivity has had on those previously digitally disenfranchised; for example, in 2016 sub-Saharan Africa typically had 1 landline but 74 mobile-connected devices per 100 people.

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1 Introduction

We are currently in a transition period for cellular connectivity, and the future of ubiquitous wireless connectivity is on the rise. Globally, the success of 2G, 3G and 4G has propelled mobile phone usage to an incredible 7.5 billion units. Shockingly, this puts more mobile devices than the world’s population. Perhaps even more impactful is the impact cellular connectivity has had on those previously digitally disenfranchised; for example, in 2016 sub-Saharan Africa typically had 1 landline but 74 mobile-connected devices per 100 people.

Looking ahead to the next decade, with the advent of 5G, wireless infrastructure will become more ubiquitous and even fully integrated into every aspect of our daily lives. 5G continues the pattern of previous cellular standards (in terms of driving bandwidth), but also extends it to more devices and usage patterns.

Key trends include:

1. Increased bandwidth demand for Enhanced Mobile Broadband (eMBB) and other applications, especially instantaneously available bandwidth driven by 10 times existing throughput or higher.

a. This will be the first driver of 5G standardization, where 3GPP has completed non-standalone (ie LTE-assisted) New Radio (NR) in 2017, and 5G standalone version will be available in 2018, as shown in Figure 1.

b. The deployment of 5G will also be phased in according to the frequency band situation, starting with the deployment of sub-6GHz and then successive bands of millimeter wave (mmWave) frequencies to support key eMBB applications at a later stage.

Figure 1: ITU and 3GPP timeline for 5G

2. With the advent of the Internet of Things (IoT) cellular network connectivity comes connecting to a huge number of devices. It is expected that there will be 50 billion cellular-connected devices by 2020. Some of these requirements can be met by existing standards, but also by existing specifications for Massive Machine Type Communication (mMTC) in Release 16.

3. New application models are also emerging, which places new demands on mobile devices and their cellular wireless infrastructure. Examples include:

a. Low bandwidth, low power requirements for connecting multiple battery powered IoT endpoints for mMTC related connectivity and monitoring;

b. High reliability, low latency cellular networks for vehicle-to-vehicle and vehicle-to-infrastructure connectivity (C-V2X) to complement existing V2X solutions

c. High reliability, low latency support for emerging applications such as telesurgery and augmented/virtual reality

The latter two categories of applications will be addressed by the upcoming 3GPP Ultra-Reliable, Low-Latency Connectivity (URLLC) standard.

4. New demands for edge analytics and mobile edge computing (MEC). The computing center of gravity is shifting from the previously estimated sending of data to centralized computing resources for processing, to a new paradigm of moving to distributed computing resources located near the origin of data generation. The reasons for this shift are manifold: the stringent latency requirements of emerging applications, the ever-increasing volume of data, and the desire to optimize scarce network resources, among many others.

2. Baseband

In this article, we consider how to successfully address the unique demands of 5G through SoC architectures with high-performance CPU subsystems and including FPGA reprogrammable accelerated hardware processing units.

The baseband takes data from a network interface (eg Ethernet) and converts it into complex samples that are transmitted to the RF front-end via the fronthaul interface for incoming/outgoing. The following high-level schematic includes a transmitter for the LTE downlink (Figure 2a), and a receiver for the uplink (Figure 2b).

(a) Downlink

(b) Uplink

Figure 2: High-level schematic of baseband processing

3. A case study of baseband L1 processing

Here, we illustrate how baseband processing (especially Layer-1) can be mapped onto key processing components such as processor subsystems, CPU and DSP cores, and fixed and flexible hardware acceleration, as shown in Figure 3 .

Figure 3: Key baseband processing components

3.1. Fronthaul (antenna interface) connection

In addition to the processing components described above, there is a flexible antenna interface function block: this is the element required to connect the baseband and the RF unit. Traditionally, this has been a Common Public Radio Interface (CPRI) and sometimes Open Base Station Architecture Initiative (OBSAI) compliant part.

However, an increasing number of schemes are moving towards specifying a more flexible fronthaul interface to allow for different mappings between the baseband and RF front-end (as shown in Figure 4). IEEE has continued to follow up on the next generation fronthaul interface NGFI (IEEE1914), including the network standard IEEE1914.1 for packet-based fronthaul transport and the Radio over Ethernet (RoE) encapsulation and mapping standard IEEE1914.1. Meanwhile, there are other industry projects that specify 5G fronthaul interfaces that can be shared, such as eCPRI.

Given the variety of specifications, standards, and requirements that fronthaul interfaces face, FPGAs are well suited to their application and are typically used to support this interface, as shown in Figure 3.

3.2. Discrete structures that can accelerate 5G time-to-market

Figure 4 maps the processing components required for 5G into a discrete architecture with separate components, including a CPU SoC, secondary FPGA acceleration, and antenna interfaces. This configuration reflects an implementation that can be deployed in 5G prototyping and early volume production until an optimized 5G application-specific integrated circuit (ASIC) can be delivered.

・The CPU SoC includes: a combination of Arm processors and DSP cores for Layer-1 processing and hardened accelerators for fixed, well-defined functions.

o In this example, it is assumed that an existing 4G ASIC SoC is available, and thus has general accelerations (eg MACSEC) as well as LTE specific accelerations: Forward Error Correction (specifically turbo codecs), Fast Fourier Transform and Discrete Fourier Transform , to support SC-FDMA on the uplink.

・Flexible antenna interface

o As mentioned earlier, the fronthaul antenna interface is well suited for FPGA implementation. This is configured online, data is sent from the RF unit (on the uplink) and then converted to a protocol such as Ethernet with standard connectivity.

・Hardware accelerated FPGA

o Auxiliary acceleration FPGAs implement all the necessary compute-intensive functions not available on baseband SoCs. This can be a 5G-specific function or a function that was not previously planned.

oIn the example shown here, a CCIX interconnect is used. The standard allows processors based on different instruction set architectures to extend the benefits of cache coherence, peer-to-peer processing to a variety of acceleration devices including FPGAs and custom ASICs.

Figure 4: Discrete structures that can accelerate 5G time-to-market

3.3. Chiplet-based 5G implementation

Figure 5 shows a similar architecture to that shown in Figure 4, but reconfigured using a system-in-package chip (chiplet) based approach. In this case, an interface that uses higher bandwidth, lower latency, and lower power consumption connects the CPU SoC die to the auxiliary hardware-accelerated chiplet. The FPGA device that supports the fronthaul connection to the RF unit can in this example, but is not packaged in it; in practice, it can be the same chiplet device as the hardware accelerated chiplet chip if sufficient resources are available.

Figure 5: Chiplet-based approach enables higher levels of integration

The two main techniques used for package integration are the use of silicon interposers or organic substrates, and some form of ultra-short-range (USR) transceivers.

3.4. Fully integrated 5G implementation

Finally, Figure 6 shows the final, most integrated baseband architecture considered in this paper. The approach includes the same processing elements as before, with the same functionality, but with an embedded FPGA (eFPGA) integrated on-chip.

Figure 6: Heterogeneous multi-core SoC for 5G baseband with monolithic integration

This tightly integrated monolithic integration approach has many advantages. Compared to chiplet-based methods, the interface has higher bandwidth, lower latency, and lower energy consumption per bit. Furthermore, resource combinations can be tailored to the specific application under consideration, thus avoiding unnecessary interfaces, memory and core logic units. This achieves the lowest unit cost of the three architectures considered above.

As mentioned earlier, the main goal now is to provide faster time to market, greater flexibility and future availability. The time-to-market is accelerated because SoCs can be taped out ahead of time because post-modifications can be made for eFPGAs (such as the emergence of Polar codes in the 5G standard) instead of ready-made ASICs. Flexibility from new or unanticipated algorithms (such as new encryption standards) can be addressed by embedded programmable logic rather than software or an external FPGA. Finally, future availability can extend the life cycle of SoCs, as high-volume emerging needs such as new standards such as URLLC and mMTC can be addressed by existing products without requiring new development.

Summarize

The tight coupling of the CPU and programmable acceleration (embedded or stand-alone FPGA) enables developers to create a single platform product that can be used in many different markets. This increases the market applicability of specific products and improves the return on development investment. This can even be repositioned (or repositioned) in the market after tape-out, i.e. the inherent flexibility provided by maximized programmability allows considerable room for innovation.

Perhaps even more important from a 5G perspective, highly programmable solutions can speed time-to-market. For example, it is no longer necessary to delay the tape-out of SoCs until the standard is finalized, and the requirements for subsequent changes can be implemented in software or programmable hardware. This is a distinct advantage for early and increasing pressures on 5G deployments and the constant emergence of new standards.