Eliminating Miller Effect Using Cascode Topology in Semiconductor Switches

“The SiC cascode topology solves the Miller capacitance problem while simultaneously enabling simple gate drive, normally-off operation, and a high-performance body diode. This differs from SiC MOSFETs, where the body diode characteristics are poor, and even from GaN HEMTs, which have high CDS. The invariance of physical characteristics leads to the Miller effect that limits high-frequency gain in thermionic devices, which also applies to semiconductor devices.

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The laws of physics cannot be defeated. Resistors necessarily dissipate electrical energy and generate heat and voltage drop. Capacitors take time to store charge and take time to release charge. Inductors take time to create an electromagnetic field and let it collapse. There’s nothing we can do about it, so since the thermionic tube was born, electronics designers have learned to work around these factors by developing clever circuit topologies. It turns out that physics is physics, and the same rules that used to apply to tubes apply to high-performance semiconductors today.

How Miller Capacitors Limit High Frequency Amplification

Take the Miller effect, for example. In the 1920s, American electrical engineer John Milton Miller discovered that when simple vacuum triodes were used as amplifiers, there was a problem due to the internal capacitance between the grid and the anode. This capacitor reduces the bandwidth of the amplifier by applying higher and higher negative feedback as the impedance of the capacitor decreases with increasing operating frequency.

Miller recognized that placing two transistors in series as shown in Figure 1, such as a cascaded transistor or cascode topology, might reduce the total capacitance from input to output. In view of the fixed voltage of the upper tube row, the cathode voltage of the upper transistor is controlled by the lower transistor. This internal capacitance and its associated effects are reduced when tetrodes with internal curtain grids are developed, allowing the construction of single-tube amplifiers that can operate at hundreds of megahertz.

Figure 1: The original cascode or cascode circuit

The return of the Miller effect

The Miller effect also returned as designers began to replace thermionic tubes with solid-state semiconductors, which once again began to limit high-frequency operation.

Why is this happening? In MOSFET-based switching circuits, the Miller effect limits switching speed because the driver circuit must charge and discharge the input capacitance in a reliable manner with low loss. The effect of this Miller capacitance, or CGD, varies with the gate voltage.

For example, consider an enhancement-mode MOSFET switch that turns off when the gate voltage is 0V. The total gate input capacitance appears as a network (see Figure 2) including CGS, CGD, CDS, load ZL, and bulk capacitance CBULK. There is also a positive voltage across the CGD. When the MOSFET is turned on, the drain voltage drops to near zero, the total capacitance becomes CGD in parallel with CGS, and there is a negative voltage across CGD compared to the off state. During switching from on to off and from off to on, the input capacitance must be swapped between these conditions.

Figure 2: The MOSFET input capacitance is the same when turned off and on

The plateau in the forward portion of the MOSFET gate switching waveform (see Figure 3) represents a transition between the two input capacitance states, as the driver suddenly has to work harder, slowing the switching transition. To exacerbate effects such as drain voltage drop, it will try to “push” negative gate voltage across the CGD against the positive on-state voltage command. This process is reversed when the driving MOSFET is turned off. CGD will try to “pull” the positive gate voltage, which is why designers dealing with MOSFETs and IGBTs are encouraged to use negative off-state gate voltages to counteract this effect. This in turn increases the power required to drive the gate.

Figure 3: Miller capacitance “platform” of gate drive voltage

Controlled gate-to-drain capacitance

The gate-to-drain capacitance, CGD, of a device is affected by the architecture of the semiconductor device and therefore varies for lateral or vertical builds. CGD can be minimized for low voltage MOSFETs, but at high voltages it can become a problem, especially when designers want to build wide-bandgap devices using materials such as silicon carbide (SiC) or gallium nitride (GaN). Some laws of physics cannot be circumvented: the switching speed of these technologies is still limited by their Miller capacitance, and the best way to combat the Miller effect is to use a cascode circuit topology.

modern cascode

Basic SiC switches use a junction FET (JFET) structure. If the JFET is built as a vertical device, its CGD may reach a favorable low point, and its drain-to-source capacitance CDS may be lower. However, JFETs are normally-on devices that have a gate of 0V and require a negative gate voltage to turn off. This is a problem in bridge circuits, where all devices default to ON for instantaneous power. It would be better to build such circuits using normally-off devices, which can be implemented by arranging Si MOSFETs and SiC JFETs in a cascode topology (Figure 4).

Figure 4: Silicon/SiC Cascode

When the MOSFET gate and source voltages are 0V, the drain voltage rises. The JFET gate is also 0V, so when the source voltage rises from the MOSFET drain voltage to 10V, the JFET sees -10V between the gate and source, so the switch turns off. When the MOSFET gate voltage is positive, it turns on, thus shorting the gate and source of the JFET, which turns on the JFET. This circuit topology creates the desired normally-off device with a MOSFET gate voltage of 0V. This topology also means that the input and output capacitors in series include CDS to achieve a JFET whose value is close to zero, reducing the Miller effect and its effect on high frequency gain.

Other advantages

When switching, the Si MOSFET drain voltage is the JFET drain voltage that “pours down” through the nearly zero JFET drain to source capacitance CDS and the MOSFET’s non-zero CDS, so the MOSFET drain remains low. This means that the MOSFET can be a low voltage type with very low on-resistance maintained between drain and source and easier gate drive. Another advantage is that the body diode of the low voltage MOSFET has very low forward voltage drop and fast recovery. JFETs do not have a body diode, so when the third quadrant reverse switch is required to conduct, as in a commutator bridge circuit or synchronous rectification, the MOSFET body diode conducts. This limits the JFET gate-source to about +0.6 V, ensuring that it is turned on as much as possible, which enables reverse current flow and low dropout.

The end of the Miller effect

The SiC cascode topology solves the Miller capacitance problem while simultaneously enabling simple gate drive, normally-off operation, and a high-performance body diode. This differs from SiC MOSFETs, where the body diode characteristics are poor, and even from GaN HEMTs, which have high CDS. The invariance of physical characteristics leads to the Miller effect that limits high-frequency gain in thermionic devices, which also applies to semiconductor devices. However, this invariance also means that the cascode-based solution to the problem works just as well in modern SiC devices as it does in older tubes. It seems that the more that changes, the more that remains the same.