Materials help image imaging to resolve contradictions in PPAC

“In the golden age of the semiconductor industry, while Gordon Moore was still drawing up a roadmap for his company, the reduction in plane size brought about simultaneous advancements in power consumption, performance, and area/cost (PPAC). However, over time, Dennard’s reduction in plane size has been hindered from helping with power consumption, and materials engineering has begun to be applied to semiconductor manufacturing to promote continued improvements in power consumption, performance, and area/cost. Among them, the high-K metal gate is the most powerful example.

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In the golden age of the semiconductor industry, while Gordon Moore was still drawing up a roadmap for his company, the reduction in plane size brought about simultaneous advancements in power consumption, performance, and area/cost (PPAC). However, over time, Dennard’s reduction in plane size has been hindered from helping with power consumption, and materials engineering has begun to be applied to semiconductor manufacturing to promote continued improvements in power consumption, performance, and area/cost. Among them, the high-K metal gate is the most powerful example.

At present, engineers generally acknowledge this contradiction: design engineers optimize power consumption and performance, while process engineers actively reduce 2D size to reduce area and cost. Regardless of logic or memory, especially when the industry’s production graphics are reduced to below 8nm, design advancements are not organically combined with process innovation. Although the size of node naming is shrinking, the shrinking speed of feature size is not as fast as before. In addition, we have also seen a sharp slowdown in the rate of cost reduction (see Figure 1).

Figure 1: The complexity of chip design leads to a slowdown in feature size reduction and an increase in cost

Q

Why is the size shrinking and not progressing as fast as it should be? Why is the cost of high-end silicon still so expensive?

A

The answer lies in the complexity of chip design-today’s chip design has many layers, and each layer must be seamlessly connected.

Take DRAM as an example. A DRAM device has about 7 key graphics layers, each layer is different (see Figure 2). In addition to the different physical structures of the shallow trench isolation (STI) layers, capacitors, bit lines, and word lines, there are also layers with high aspect ratios, which makes it more and more difficult to align the upper layer with the next layer. These different feature patterns must be perfectly imaged and aligned to ensure the normal operation of the device. However, the simultaneous shrinking of these distinct graphic layers brings greater complexity to the realization of the process. Once the process fails to meet the requirements, the graphic edge flatness error (EPE) will increase resistance and reduce performance, eventually leading to yield loss and device failure.

Figure 2: Challenges to pattern reduction and alignment generated in different device layers of DRAM

Therefore, when the roadmap is blocked, we need a “new strategy” to improve chip performance, power, area cost, and time to market (PPACt).

New strategy

New computing architecture

New devices and 3D structures on the chip

New Materials

New method for continuous 2D size reduction (topic of this blog)

Heterogeneous design and advanced packaging

From the equipment point of view, we need to do more than just introduce new films or improve individual processes such as etching. We also need to consider comprehensively and develop corresponding supporting technologies according to the needs of each device.

This evolution from a single process to a material integration solution can also help customers reduce process steps, reduce research and development costs and time, and ultimately accelerate the speed of products to market. The following are the three innovative technologies that I announced at the SPIE Advanced Lithography Conference held earlier this year. These technologies demonstrate how chip manufacturers can benefit in many ways through the use of a holistic approach to advanced graphics imaging.

Right-angle sidewall mask technology

Right-angle sidewall mask technology is an application of two-time self-aligned pattern imaging (SADP) and four-time self-aligned pattern imaging (SAQP). Sidewall deposition and sidewall etching are very challenging. One of the reasons is that the materials used are relatively soft, and the top and bottom are easy to arc (not easy to form right angles). This will lead to unevenness and pitch drift, which in turn will cause lithography registration errors and vertical deviation EPE-at smaller process nodes, this type of fluctuation problem will be more serious.

Chip manufacturers usually solve the fluctuation problem by adding additional process steps, which will also increase cost and complexity. In addition, although the additional hard mask etching and core mask etching process can reduce the volatility from the first sidewall etching, it will also reduce the realization of the critical dimension (CD) desired by the designer. In other words, the process steps to solve EPE are accompanied by performance compromises, which will reduce the level of control over the design results.

A new process developed by Applied Materials is able to optimize the sidewall material so that it can be more adapted to the etching process to achieve better alignment effects (see Figure 3). This process first uses the CVD process to deposit amorphous silicon with ALD-like accuracy, and then uses our Centris® Sym3™ etching system for pattern imaging and VeritySEM® system measurement. The solution we provide allows chip manufacturers to use traditional process steps while maintaining the fidelity of graphic imaging, reducing the number of SAQP steps from 15 to 11 by removing unnecessary deposition and etching steps . As a whole, it helps customers to reduce the size of graphics in a more cost-effective and efficient way.

Figure 3: Compared with the traditional process, Applied Materials’ unique sidewall material can achieve better uniformity and alignment effect

Lateral etching technology

Another unique technology developed by Applied Materials is called lateral etching. When using traditional photolithography and etching processes, designers can only combine various features with a limited degree of compactness. This is called the minimum line spacing in the horizontal direction, and the top and bottom thickness in the vertical direction. When EUV is used, the current minimum line spacing is about 36nm, and the top and bottom thickness is about 40nm. If these line spaces are too large for the design, the chip manufacturer will have to invest in additional graphic imaging steps-either by adding mask cut-off or selective masking, or by adding EUV lithography-etching steps. The only alternative is to continue to use a larger chip area, but this will increase the chip area/cost ratio.

Etching has always been done from top to bottom. However, Applied Materials has developed an innovative lateral etching technology that can perform etching at a 45-degree angle, giving designers a new degree of freedom (see Figure 4). By controlling the etching direction, we can shrink CD laterally while maintaining the thickness of the longitudinal mask. Facts have proved that we have been able to achieve the vertical film thickness of about 20nm under the horizontal CD independent reduction.

Figure 4: Applied Materials’ innovative lateral etching technology can reduce the number of EUV masks by 50% or more

Lateral etching allows designers to reduce process steps and make various features more closely integrated, thereby increasing area density and benefiting more device applications. We coordinate this process with our Producer® Precision™ CVD carbon and silicon hard masks, Sym3™ etching, and PROVision™ electron beam measurement and defect control to achieve advanced graphics imaging solutions and give designers the opportunity Reduce the number of EUV masks by 50% or more.

Selective process technology

The third technology we announced at the SPIE Advanced Lithography Conference is a selective material deposition process. This process can solve the problem of EPE and improve the pattern reduction effect by controlling the dislocations between different device layers. Unlike traditional deposition, selective processing (deposition/etch) processes are used to eliminate EPE, thereby reducing the size of the design rule and reducing the number of masks.

For selective deposition to effectively reduce EPE, there are two key challenges that must be overcome. First, the surface of the wafer must be clean enough to allow selective deposition on the desired material (rather than other materials). Any defects on the wafer will compromise selectivity. The second challenge is to effectively control the selectively deposited materials, which will not only grow vertically, but also grow horizontally. Due to the aforementioned challenges, most selective depositions are limited to very thin layers.

Applied Materials has developed a collaboratively optimized selective processing solution using Endura® deposition platform, Producer® Selectra™ selective etching technology, and PROVision™ electron beam measurement and defect detection technology. We have demonstrated this process in the through-hole process flow shown in Figure 5. We first start with the metal layer and proceed with the selective growth of materials; then fill and planarize; then proceed with the traditional process of titanium nitride (TiN) hard mask, and laminate the through-hole photoresist; then continue with the through-hole photolithography , And then turn to etching. When we etch in one direction, it acts as a mask for the TiN that defines the trench. Our newly developed material has high etching options. This means that the via will be perfectly etched into a rectangle that defines where the two metal layers intersect each other. This technique eliminates EPE by maximizing the size of the vias and also eliminates the problems associated with the reduction of interconnect size.

If designers have a through-hole layout higher than the minimum resolution of photolithography, they must use multiple photolithography-etch through-hole processes. Using our new process, customers can define a larger via and create vias only at the intersection between two metal layers. In this way, we can perfectly align the bottom and top device layers, thereby saving process steps and achieving large process latitude and low impedance vias (see Figure 6).

Dan Hutcheson, Chairman and CEO of VLSIresearch, said: “The real innovation lies in the fact that Applied Materials is able to establish a new through-hole process to reduce EPE compared with the traditional multi-pattern imaging multiple-image synthesis cutting mask method. In addition to improving the yield rate, reducing EPE can also increase the revenue per wafer, because the reliability and performance of the chip are improved, and the chip’s reliability and performance Power consumption is lower.”

Figure 6: Compared with traditional processes, self-aligned processing with complete selectivity can reduce resistance, increase yield, and reduce the number of masks

All in all, this “new strategy” has brought us new tools to accelerate the industry roadmap, including addressing the challenge of size reduction from a global perspective, in order to solve PPACt’s problems at the same time. By collaboratively optimizing the applied materials company’s wide-ranging technology, we can provide new materials to reduce the size of new graphics, so that cost-effective scaling can continue without affecting the design. Welcome to the era of materialized graphic imaging!